For those who read here often, there are clear signs that the FPGA is set to become a compelling acceleration story over the next few years.
From the relatively recent Intel acquisition of Altera by chip giant Intel, to less talked-about advancements on the programming front (OpenCL progress, advancements in both hardware and software from FPGA competitor to Intel/Altera, Xilinx) and of course, consistent competition for the compute acceleration market from GPUs, which dominate the coprocessor market for now.
Last week at the Open Compute Summit we finally got a glimpse of one of the many ways FPGAs might fit into the hyperscale ecosystem (along with other future hardware insight) with an announcement that Intel will be working on future OCP designs featuring an integrated FPGA and Xeon chip. Unlike what many expected, the CPU mate will not be a Xeon D, but rather a proper Broadwell EP. As seen below, this appears to be a 15-core part (Intel did not confirm, but their diagram makes counting rather easy) matched with the Altera Arria 10 GX FPGAs.
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