Moore’s law has driven the semiconductor industry to continue downscaling the critical size of transistors to improve device density. At the beginning of this century, traditional scaling started to encounter bottlenecks. The industry has successively developed strained Si/Ge, high-K/metal gate, and Fin-FETs, enabling Moore’s Law to continue.
Now, the critical size of FETs is down to 7 nm, which means there are almost 7 billion transistors per square centimeter on one chip, which brings huge challenges for fin-type structure and nanomanufacturing methods. Up to now, extreme ultraviolet lithography has been used in some critical steps, and it is facing alignment precision and high costs for high-volume manufacturing.
Meanwhile, the introduction of new materials and 3D complex structures brings serious challenges for top-down methods. Newly developed bottom-up manufacturing serves as a good complementary method and provides technical driving force for nanomanufacturing.
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