The manipulation of mechanical strain in materials, also known as strain engineering, has allowed engineers to advance electronics over the past decades, for instance enhancing the mobility of charge carriers in devices. Over the past few years, some studies have tried to devise effective strategies to manipulate strain in two-dimensional (2D) semiconductors that are compatible with existing industrial processes.
Researchers at Stanford University recently introduced a CMOS-compatible approach to engineer the tensile strain (i.e., stretchiness) in monolayer semiconductor transistors.
This approach, outlined in a paper published in Nature Electronics, relies on the use of silicon nitride capping layers that can impart strain on monolayer molybdenum disulfide (MoS2) transistors integrated on silicon substrates.
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